Determining control signals for a cycle of instruction

Cheatsheet

- Singlecycle

- Multicycle

 

Properly solving it

 

Look at the question above. It's quite intimidating at the start because it feels very difficult to parse through. Control signals are referring to the orange lines in the diagram below. 

The red dotted lines are drawn so that it's clear what needs to be considered in each cycle. The territory contained within that red dotted line is what happens in one cycle. The left red box is for the cycle that fetches the instruction, and you can see that there are 3 signals to be determined: IorD, MemRead, MemWrite. If you wanted to fetch an instruction from PC, then you need to set IorD to 0 to feed PC into Address, and set MemRead to 1, and set MemWrite to 0. In this cycle, the instruction that was read from the PC address will be stored in IR and MDR. As fetch cycle is only concerned with the orange control signals that end up in red box, we can set 'dont-care (or x)' in the other control signals. However, there's a caution:

 

You need to make sure that there's no writes triggered unnecessarily - PCWrite, PCWriteCond, MemWrite, RegWrite always have to be set to a value for any cycle, as otherwise it results in random values being written.

 

 

The rest is pretty straightforward. 

 

It's clearer with the following table, that specifies what happens in each cycle.